In general, the higher density a semiconductor memory device has, the lower power consumption the semiconductor memory device requires. To satisfy this requirement, a memory cell array composed of a plurality of memory cells is divided into a plurality of sub-array blocks. Thus, when a predetermined memory cell is selected, the semiconductor memory device may suppress power consumption by enabling the memory cell array by the sub-array block unit. The pursuit for the sub-array block will be considered more and more, as the density of the semiconductor memory device increases. On the other hand, when data is read out or written into the semiconductor memory device, all bits of an address are to be decoded so as to select a given memory cell. However, the time delay of the address decoding operation causes operation speed of the semiconductor memory device to be reduced. Therefore, it is desirable that the semiconductor memory device have an address decoding circuit which does not reduce operation speed of the semiconductor memory device.
FIG. 1 is a schematic block diagram showing a conventional decoding device for a semiconductor memory. A memory cell array 10 is composed of n large blocks LB1-LBn, each of the large blocks having m small blocks SB11-SBnm in which memory cells are arranged in matrix form. In the drawing, reference numeral 20 represents a row address buffer, reference numeral 30 a row predecoder, reference numeral 40 a row decoder, reference numeral 50 a column address buffer, reference numeral 60 a column predecoder, reference numeral 70 a small block predecoder, reference numeral 80 a large block predecoder, reference numeral 90 a column decoder, and reference numeral 100 n reading/writing circuits R/W1-R/Wn each corresponding to n large blocks LB1-LBn.
FIG. 2 shows the operational timing diagram for a decoding operation conducted by the device of FIG. 1. Row predecoder 30 decodes i address signals Ax1-Axi inputted from row address buffer 20 and outputs h address signals to row decoder 40. Thereafter, row decoder 40 outputs one of k row address signals to memory cell array 10. Column address buffer 50 buffers j address signals Ay1-Ayj and outputs p address signals to column predecoder 60, q address signals to small block predecoder 70, and r address signals to large block predecoder 80. Column predecoder 60, small block predecoder 70, and large block predecoder 80, respectively, decode p, q, and r address signals and respectively output l, m, and n address signals to column decoder 90. Column decoder 90 outputs one of b address signals to memory cell array 10. The memory cells connected to a given word line are selected by row decoder 40, and a specific large block is selected by the upper bits of the address signal outputted from column decoder 90. Subsequently, the small blocks in the selected large block are selected by the next upper bits of the address signal, and columns in the selected small blocks are ultimately selected by the lower bits of the address signal. Typically, reading/writing circuits R/W1-R/Wn are divided so as to have the same number as that of large blocks LB1-LBn. That is, each of large blocks LB1-LBn serves as a unit of dividing reading/writing circuits R/W1-R/Wn. D-bit data is inter-transferred between large blocks LB1-LBn and reading/writing circuits R/W1-R/Wn. Therefore, upon the data reading operation, if a given memory cell is selected in the same manner as previously stated, a selected one of reading/writing circuits R/W1-R/Wn selected by the address signal outputted from large block predecoder 80, corresponding to large blocks LB1-LBn is selected and thereafter, data of the selected memory cell is read out to transfer through a data input/output line I/O. On the contrary, in the case of performing a data writing operation into a predetermined memory cell, the memory cell in which data is to be written is selected in the same manner as discussed above. As shown in FIG. 2, reading/writing circuit selection signal 311 and large block selection signal 312 are enabled by large block selection address signal 301, thereby causing a predetermined reading/writing circuit and large block to be selected, respectively. Then, small block selection signal 313 is enabled by large block selection signal 312 and small block selection address signal 302, thereby causing the small block in the selected large block to be selected. Thereafter, column selection signal 314 is enabled by small block selection signal 313 and column selection address signal 303, thereby causing a desired column to be ultimately selected.
If in a conventional decoding apparatus and method a column is to finally be selected, firstly a large block is selected by the upper bits of an address signal. Secondly, the small blocks in the selected large block must be selected. Lastly, a predetermined column is selected. In this case, address signals for selecting reading/writing circuits must be decoded in the same manner as the large blocks discussed above. The same address bits for decoding large blocks, as shown in FIG. 1, should also be used in the reading/writing circuits. Accordingly, it is required that a decoding path for receiving a corresponding address should be constructed. Such a requirement, however, produces a problem in that the time delay increases due to the signal passing through many logic gates and additionally, this solution increases the non-effective layout area.